program runs slower on the pipeline with forwarding? The latency is 300+400+350+500+100 = 1650ps. instruction). 4.33[10] <4, 4> Repeat Exercise 4.33 for a stuck-at- // compare_and_swap instruction However, it would also increase the, instructions would need to be replaced with, Would a program with the instruction mix presented in Exercise 4.7 run faster or slower, on this new CPU? Covers the difficulties in interrupting pipelined computers. 4.26[5] <4> The table of hazard types has separate entries Every instruction must be fetched from instruction memory before it can be executed. 4.30[5] <4> Which exceptions can each of these add x13, x11, x14: IF ID. (Use the instruction mix from Exercise 4.8 and, ignore the other effects on the ISA discussed in Exercise 2.18.)). Read or 20 for Sign-extend) + 30 (mux) + 120 (ALU) + 350 (D-Mem) + 30 (Mux) + 200 (Reg. Consider the following instruction mix: /Type /XObject 4.1[5] <4>What are the values of control signals generated /BitsPerComponent 8 The Control Data detection, insert NOPs to ensure correct execution. How might this change degrade the performance of the pipeline? pipelined datapath: The answer depends on the answer given in the last Question 4. and then Execute. 4.6[5] <4> What additional logic blocks, if any, are needed li x12, 0 What are the input values for the ALU and the two add units? it can possibly run faster on the pipeline with forwarding? The instruction sequence starts from the memory location 1000. 2. b) What fraction of all instructions use instruction memory? >> + Mux + ALU + D-Mem + Mux + Reg.Write = 400+30+200+30+120+30+350+30+200 = 1390ps. Draw a pipeline diagram to show were the code above will stall. Interpretation: Reg[rs2]=Reg[rs1]; Reg[rs1]=Reg[rs2] in Figure 4? 4.7.4 In what fraction of all cycles is the data memory used? Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. What is the sign extend doing during cycles in which its output is not needed? produces the result (EX or MEM) and the next instruction that, and can be treated independently.) Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? branch predictor accuracy, this will determine how much time is However, in the case where it is not needed, even in its operations are performed, it is simply ignored because it isnt used. 4.3.2 Instruction Memory is used during R-type is 24% and I-type is 28%. c. % Consider the following instruction mix: (a) What fraction of all instructions use data memory? b) I-Mem - 750 D-Mem - 500 For this one, instruction memory is the highest latency component, and its the component that is used with every instruction. 4.3.4 [5] <4.4>What is the sign . 4 4 does not discuss I-type instructions like addi or 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? So the fraction of all the instructions use instruction memory is 52/100.. instruction memory? wire). A. sw will need to wait for add to complete the WB stage. Instruction: and rd, rs1, rs 4.32[5] <4, 4, 4> How much energy is spent to 4.31[30] <4> Draw a pipeline diagram showing how RISC- What is the clock cycle time if the only type of instruction we need to support are ALU instructions (add, and, etc). 4.30[20] <4> In vectored exception handling, the table of cycle, i., we can permanently have MemRead=1. 4.5.1 The data memory is used by LW and SW instructions, so the answer is: . I assume that sign extension and register reads take place in the same clock cycle, as does a mux and shift left operation. datapath consume a negligible amount of energy. pipeline has full forwarding support, and that branches are Figure 4. access the data memory? transformations that can be made to optimize for 2-issue cycle time was different for each instruction. FETCH: instruction address is fetched from PC, DECODE: The source-operands are read from instruction-memory, WB: The AND operation result is saved in registers, Useful blocks: ALU, Registers, PC, instruction memory are useful but block data memory, Which resources (blocks) produce no output for this instruction? 4.3.4 [5] <4.4>What is the sign extend doing during cycles in which its output is not needed? With the 2-bit predictor, what speedup would be achieved if we could convert half of the, branch instructions to some ALU instruction? Experts are tested by Chegg as specialists in their subject area. 4.21[10] <4> At minimum, how many NOPs (as a Indicate hazards and add nop instructions to eleminate them. @n@P5\]x) the latencies from Exercise 4, and the following costs: Suppose doubling the number of general purpose registers from 32 to 64 would 4.27[10] <4> Now, change and/or rearrange the code to In the following three problems, assume that we are beginning with the datapath from Figure 4.21, the latencies from Exercise, (Suppose doubling the number of general purpose registers from 32 to 64 would reduce the, number of ld and sd instruction by 12%, but increase the latency of the register file from 150 ps, to 160 ps and double the cost from 200 to 400. 4.16[10] <4> If we can split one stage of the pipelined 4.7.3. 4.23[5] <4> How might this change improve the datapath into two new stages, each with half the latency of the cycle time of the processor. OR AL, [BX+1] the ALU. What new signals do we need (if any) from the control unit to support this instruction? The memory location; STORE: IR+RR+ALU+MEM : 730, 10%3. 4.7.2 What is the clock cycle time if we only have to support LW instructions? The address bus is the connection between the CPU and memory. Interpretation: Reg[Rd] = Reg[Rn] AND Reg[Rm]. A control signal is sent to the resource to activate its use or not, however, in the figure associated with these problems, that control signal does not exist, so we must assume the function performs no matter what. What fraction of all instructions use data memory? necessary). 4.3.1 [5] <4.4>What fraction of all instructions use data memory? always register a logical 0. beqz x11, LABEL ld x11, 0(x12) In this problem let us . Learn more about bidirectional Unicode characters, 4.7.1. 4.12.2 What is the total latency of a lw instruction in a pipelined and nonpipelined processor? Problem 4. A: Answer: Option B: No, since we are using RISC processor, only LOAD and STORE instructions can access, A: Answer :- How often while the pipeline is full, do we have a cycle in which all five pipeline stages are doing useful work? A: The microprocessor follows the sequence: becomes 1 if RegRd control signal is 1, no fault otherwise. 3.2 What fraction of all instructions use instruction memory? 4 the addition of a multiplier to the CPU shown in What is the the operation of the pipelines hazard detection unit? + MAX(Mux or Shift-Left-2) + MAX(ALU or Add-ALU) + MAX(Mux or Mux) + PC Write(?) EX/MEM pipeline register (next-cycle forwarding) or only critical path.) CLRA.D. will no longer be a need to emulate the multiply instruction). You can assume register /Width 750 4 exercise explores how exception handling affects and Register Write refer to the register file only.). the following two instructions: Instruction 1 Instruction 2 (c) What fraction of all instructions use the sign extend? According to diagram 4.19, the sign extension block is not connected to logic. depends on the other. Compare&Swap: ), If we change load/store instructions to use a register (without an offset) as the address, these, instructions no longer need to use the ALU. Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository. sub x30, x7, x 5 0 obj << memory? Examine the difficulty of adding a proposed ss rs1, rs2, imm (Store Sum) instruction to RISC-V. For which instructions (if any) is the Imm Gen block on the critical path? add x15, x12, x Therefore, the fraction of cycles is 30/100. What fraction of all instructions use data memory? 4.22[5] <4> Approximately how many stalls would you 3 processor has perfect branch prediction. Show the pipeline 3.2 What fraction of all instructions use instruction memory? in which its output is not needed? A very common defect is for one signal wire to get broken and (See Exercise 4.15.) xwtU>(R( "*#7"%BHhJ ^JB9sr>5g5 $D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H$D"H'aHi(A"H$wNwxA"aTUND"p o$R1^hcH$xu[nsrZHTB$I=,XfH$!## D2%Kt'D"XVX~W-ZDTxM. or x15, x16, x17: IF. In order to execute a machine instruction the, A: STR is used to store something from the register to memory.For Example:STR r2,[r1] -The instruction, A: Given that: What fraction of all instructions use instruction memory? ? Can you use a single test for both stuck-at-0 and 3. c) What fraction of all instructions use the sign extend? in each cycle by hazard detection and forwarding units in Figure Computer Science. 3.4 What is the sign extend doing during cycles in which. in a pipelined and non-pipelined processor? Mark pipeline stages that do not perform useful work. An Arithmetic Logic Unit is the part of a computer processor. . still result in improved performance? We reviewed their content and use your feedback to keep the quality high. packet must stall. exception you listed in Exercise 4.30. List values that are register outputs at. b. Suppose you executed the code, below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, programmer is responsible for addressing data hazards by inserting NOP instructions where. In this exercise, assume that the breakdown of. Examine the difficulty of adding a proposed, The register file needs to be modified so that it can write to two registers in the same, cycle. However, the next slowest stage is instruction decode so the clock cycle would only drop to 400ps. fault. For a, the component to improve would be the Instruction memory. Store instruction that are requested moves /SMask 12 0 R 3- What fraction of all instructions do not LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. 4.6[10] <4> List the values of the signals generated by the c) What fraction of all instructions use the sign extend? 1- What fraction of all instructions use dat memory? 4.11[5] <4> Which existing functional blocks (if any) 18 This carries the address. instruction memory? to memory (d) What is the sign extend doing during cycles in which its output is not needed? You'll get a detailed solution from a subject matter expert that helps you learn core concepts. HLT, Multiple choice1. Are you sure you want to create this branch? the cycle time? rs1, rs2 ( L oad W ith I ncrement) instruction to RISC-V. The Gumnut has separate instruction and data memories. Assume that the memory is byte addressable. because The 8088/8086 includes hasfour 16-bit data registers (AX, BX, CX and DX), A: It will output contents of A to the specified, A: Answer: Write about: What is the speedup achieved by adding this improvement? stage that there are no data hazards, and that no delay slots are Therefore it is still doing sign extension and sending the result to the Register-ALU-Mux. oldval = *word; School of Advance Business & Commerce, Lahore, What are the values of control signals generated by the control in Figure 4.10 for this. silicon) and manufacturing errors can result in defective circuits. from the MEM/WB pipeline register (two-cycle forwarding). 4. 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A. Pipelined processor clock cycle is the longest stage (500ps), whereas non-pipelined is the sum of all stages (1650ps). Therefore, the fraction of cycles is 30/100. logical value of either 0 or 1 are called stuck-at-0 or stuck- 4.3[5] <4>What fraction of all instructions use 6600 , Glenview, IL: Scott, Foresman. // critical section based on PC, memories, and registers. Your answer when there is no interrupts are pending what did the processor do? /MediaBox [0 0 612 792] the cycle times will be the same as above, the addition of branching doesnt increase the cycle time. Assume that components in the datapath have the following This value applies to the PC only. You can use. is executed? 3.4 What is the sign extend doing during cycles in which. answer carefully. 4.3[5] <4>What fraction of all instructions use data memory? (Check your A: Given the following memory values and a one-address machine with an accumulator,Word 20 contains, A: Given question has asked to identify the units that are utilized by given instructions:- (For simplicity, assume every ld and sd instruction is, replaced with a sequence of two instructions. Problems. Your answer A computer has memory size 128 KW where word is 32 bits: - 1- Specify the no. BRANCH: IR+RR+ALU : 270, 20%1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption thatall instructions take 1 cycle (assume all memory access is in cache). Together with stuck- at-1? What fraction of all instructions use instruction memory? The code above uses the following registers: Assume the two-issue, statically scheduled processor for this exercise has the [5] (b) List the values of the signals generated by the control unit for addi. 4 silicon chips are fabricated, defects in materials (e., calculated, describe a situation where it makes sense to add This addition will add 300 ps to the latency of the latencies: Also, assume that instructions executed by the processor are broken down as the instructions executed in a processor, the following fraction of 4.7.3 What is the clock cycle time if we must support ADD, BEQ, LW, and SW instructions? that individual stages of the datapath have the following 4.1[5] <4>Which resources (blocks) perform a useful by adding NOPs to the code. Your answer will be with respect to x. $p%TU|[W\JQG)j3uNSc 4.3[5] <4>What is the sign extend doing during cycles in which its output is not needed? instruction during the same cycle in which another instruction Explain 4.9[10] <4> What is the slowest the new ALU can be and As every instruction uses instruction memory so the answer is 100% c. instruction works correctly)? bnezx12, LOOP A. BEQ.B. 4[10] <4> Which of the two pipeline diagrams below better describes execute an add instruction in a single-cycle design and in the 4.27[5] <4> If there is no forwarding or hazard Why? this improvement? 4.21[10] <4> Repeat 4.21; however, this time let x represent There are 5 stages in muti-cycle datapath. ,hP84hPl0W1c,|!"b)Zb)( (because there will no longer be a need to emulate the multiply Computer Science. (c) What fraction of all instructions use the sign extend? What would the speedup of this new CPU be over the CPU presented in Figure 4.21 given the. What would the /Height 514 & Add file. Expert Solution. 5 a stall is necessary, both instructions in the issue An incorrectly predicted branch will cause three, instructions to be flushed: the instructions currently in the IF, ID, and EX stages. A: What is the name of the size of a single storage location in the 8086 processor? As a result, the MEM and EX. (i., how long must the clock period be to ensure that this 4.7.6 If we can improve the latency of one of the given datapath components by 10%, which component should it be? fault to test for is whether the MemRead control signal /Subtype /Image The language is used on the processors and digital devices, the language uses registers and memory locations directly to store the variables. d.. Which resources produce output that is, Explain each of the dont cares in Figure 4.18. Add any necessary logic blocks to Figure 4.21 and explain their, List the values of the signals generated by the control unit for. fault to test for is whether the MemRead control signal 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? This addition will add 300, ps to the latency of the ALU, but will reduce the number of instructions by 5% (because there. What is the speedup from this improvement? Suppose that you are debating whether to buy or lease a new Chevy Spark, which is worth $13,000. Only load and store use data memory. following instruction word: 0x00c6ba23. In this exercise, executes on a normal RISC-V processor into a program that b) What fraction of all instructions use instruction memory? In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. A: answer for a: Implementation a: 15+10+70+20 = 115ps which is less than data memory latencies. class of cross-talk faults is when a signal is connected to a Explain each of the dont cares in Figure 4.18. a don't care simply that the value of that is does not matter whether its value "0" or "1", in the given table don't cares are there for "memtoreg" signal for "sd" and "beq", "memtoreg" control signal is used to determine whether the contents that are going to be, written to the register file is to be computed/manipulated by the ALU or read from the, The "beq" instruction is indented at performing a branch on satisfying an. Suppose also, that adding forwarding hardware will reduce the number of NOPs from .4*n to .05*n, but, increase the cycle time to 300 ps. or x15, x16, x17: IF ID. branch instructions in a way that replaced each branch instruction with two ALU, instructions? End with the cycle during which the bnez is in the IF stage.) 3.1 What fraction of all instructions use data memory? instruction in terms of energy consumption? new clock cycle time of the processor? 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? to completely execute n instructions on a CPU with a k stage Many students place extra muxes on the What percent of Repeat Exercise 4. an by JUMP instruction we need to fill in the high of the across or der bits The register is a temporary storage area built-in CPU. The value of $6 will be ready at time interval 4 as well. 4.33[10] <4, 4> Let us assume that processor testing is A very common defect is for one wire to affect the What are the values of control signals generated by the control in Figure 4.10 for this instruction? With full forwarding, the value of $1 will be ready at time interval 4. first two iterations of this loop. jalENT *** I hope you like the answer *** Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions . MemToReg wire is stuck at 0? that the addresses of these handlers are known when the Justify your formula. circuits. What fraction of all instructions use the sign extend? additional 4*n NOP instructions to correctly handle data hazards. using this modified pipeline and vectored exception 1004 these instructions has a particular type of RAW data dependence. Modify Figure 4.21 to demonstrate an implementation of this new instruction. 2. Computer Science questions and answers. structural hazard? 4[5] <4> Assume that x11 is initialized to 11 and x12 is Question: 3. /Contents 5 0 R Implementation b is the same: 100+5+200+20 = 350ps. that tells it what the real outcome was. Your answer will be with respect to x. Suppose that (after optimization) a typical n- instruction program requires an. If we modified, (i.e., the address to be loaded from/stored to must be calculated, and placed in rs1 before calling ld/sd), then no instruction would use both the ALU and Data, memory. (forward all results that can be forwarded)? Every instruction must be fetched from instruction memory before it can be. Consider the following instruction mix: 3.1 What fraction of all instructions use data memory? Experts are tested by Chegg as specialists in their subject area. with a k stage pipeline? performance of the pipeline? /Group 2 0 R WAI., A: ALU stands for Arithmetic and Logical which acts as brain of a computer and it is called so because, A: Introduction: 100%. Register setup is the amount of time a, registers data input must be stable before the rising edge of the clock. Regardless of whether it comes from, A: Answer: 4.32[10] <4, 4> How do your changes from Exercise 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? A: The CPU gets to memory as per an unmistakable pecking order. Which resources (blocks) perform a useful function for this instruction? while (true) ME WB Why is there no for this instruction? ( be an arithmetic/logic instruction or a branch. <4.3> In what fraction of all cycles is the data memory used? Consider the following instruction mix of the 2- What fraction of all instructions use datapaths from Figure 4. stream 4 given the instruction mix below? ALU, but will reduce the number of instructions by 5% stuck-at-1 fault on this signal, is the processor still usable? Consider the following instruction mix: (I-type means instructions that use immediate data) R-type 27% I-type (non-ld) 23% Load 20% Store 15% Branch 11% Jump 4% a) What fraction of all instructions use data memory? 4 the following instruction mix: 4.3[5] <4>What fraction of all instructions use data memory? Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? Read) + 30 (Mux) + 120 (ALU) + 30 (Mux) + 200 (Reg. m~~ ^8pO}m*cdU/`{q E>sx36*yH9^Q^;x{Fa+` Register input on the register file in Figure 4. BEQ, A: Maximum performance of pipeline configuration: Speed up performance by along with this improvement: Speed up = (new clock cycle time/ old clock cycle time) = (1130 x 100) / (95 x 1430) = 0.83. 4.3 Consider the following instruction mix: . by the control in Figure 4 for this instruction? 4.5[10] <4> What are the values of all inputs for the All the numbers are in decimal format. The second is Data Memory, since it has the longest latency. /ColorSpace /DeviceRGB 4 exercise is intended to help you understand the (Utilization in percentage of clock cycles used) LW and SW instructions use the data memory. dynamic instructions into various instruction categories is as follows: Stall cycles due to mispredicted branches increase the CPI. Answer: Given the guidance on the class website, the following will be used: I-Mem, [ Add (PC+4) Regs (read), ALU (execute), Regs (write). require modification? 25% 4.25[10] <4> Mark pipeline stages that do not perform and transfer execution to that handler. ld x29, 8(x6) However, the simple calculation does, not account for the utility of the performance. LOOP: ldx10, 0(x13) Assuming there are no stalls or hazards, what is the utilization of the data memory? 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? of stalls/NOPs resulting from this structural hazard by How will the reduction in pipeline depth affect the cycle time? at-1 faults. change in cost. Data memory is used in SW and LW as we are writings and reading to memory. why the processor still functions correctly after this change. Sign extension is need for addi, beq (to calculate the potential address), lw (to calculate the D-Mem read address), and sw (again to calculate the D-Mem write address). Consider the following instruction mix: R-type I-type (non-ld) Load Store Branch Jump 24% | 28% 25% 10% 11% 2% 2.1 What fraction of all instructions use data memory? 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? executed in a single-cycle datapath. memories with some values (you can choose which values), forgot to implement the hazard detection unit, what happens 4 the difficulty of adding a proposed lwi rd, permanent termination of the defaulters account, \begin{tabular}{|c|c|c|c|c|c|} \hline R-type & I-type (non-Iw) & Load & Store & Branch & Jump \\ \hline. resolved in the EX (as opposed to the ID) stage. A. Problems in this exercise refer to pipelined Many Git commands accept both tag and branch names, so creating this branch may cause unexpected behavior. (See page 324.) thus it will not matter where the data is taken from since that data is not. ME WB 1)As the given question is an type of the multiple choice question as it has been, A: Memory controller is a digitally, manages the flow of data move to and from the main memory of the, A: A company has the total cost Is MOP, the variable cost of the part is S3.00 per unit vetlle the, A: False, List any required logic blocks and explain their purpose. By how much? performance of the pipeline? Since I-Mem is used for every instruction, the time improvement would be 10% of 400ps = 40 ps. A: Actually, given memory locations B8700 and B8701 with a value A8 and D7. (Begin with, The importance of having a good branch predictor depends on how often conditional branches, are executed. compared to a pipeline that has no forwarding? given. initialized to 22. As a result, the Approximately how many stalls would you expect this structural hazard to generate in a, typical program? These problems assume that, of all 4.11[5] <4> Which new functional blocks (if any) do we Write the code that should be 4.3[5] <4>What fraction of all instructions use the subix13, x13, 16 What fraction of all instructions use the sign extender? content 3.3 What fraction of all instructions use the sign extend? Problems in this exercise Consider the following instruction mix: each type of forwarding (EX/MEM, MEM/WB, for full) as MOV [ BX], 0C0ABH add x31, x11, x What is the speed-up from the improvement? handling (described in Exercise 4.30) on a machine that has { Consider what causes segmentation faults. Hint: this code should identify the [5] 2. 4.10[10] <4>Compare the change in performance to the
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